Microsilicon Tech

Fan-Out Wafer Level Packaging (FOWLP) offers numerous   performance and cost advantages in terms of smaller form factor and thinner   package, higher I/O density, multi-die solutions, and more.




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MST North Process is an ideal   solution for high density I/O SiP application.   The die is placed on the carrier with face   up,  it providing the design   flexibility to accommodate an unlimited number of interconnects between the   package and the application board for maximum connection density, finer   line/spacing, improved electrical and thermal performance and small package   dimensions to meet the relentless form factor requirements and performance   demands of the mobile and wearable market. 

●Adaptable for 7nm-65nm dies

●2~6 dies stackable
●Package on Package
●PKG height 0.5mm +  (Depends on   thickness of die)
●RDL min width/space ~ 2-10um / 2-10um 
●15x15mm supports ~ 1500+ pins






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MST South Process is specially   designed for high frequency RF and medium density I/O SiP application.   The die is placed on the carrier with face   down,  the RDL providing the flexibility  for RF trace design to accommodate an   unlimited  shape of trace for high   frequency over 60GHz, the antenna could be integrated in the package as well.   It improved electrical and thermal performance and small package dimensions   to meet the demands of the radar and next generation communication   market. 

●Adaptable for 16nm-65nm dies
●2 dies stackable
●4X4 – 14X14mm package size
●PKG height 0.5mm +  (Depends on   thickness of die)

●RDL min width/space ~ 10-15um / 10-15um 
●6x6mm supports ~100+ pins

●8x8mm supports ~200+ pins